Job Description: Additional Comments: Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead. Candidate should have minimum 4+ years of hands-on ...
Job Description: Additional Comments: Std cell layout Development of the standard cell library from scratch and support of existing libraries Characterization and views generation of the libraries with several custom PVT corners. Mode...
Job Description: DFT Engineers Desired Skills and Experience: B. Tech. / M. Tech. with 4+ years of experience as a DFT Engineer In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay t...
Job Description: Additional Comments: Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead. Candidate should have minimum 3+ years of hands-on...
Job Description: Analog Circuit Design Candidate should work independently on block level and chip level Analog circuit design, coordinating with the project lead. Candidate should have minimum 3+ years of hands-on experience in Analog...
Job Description: IO Layout Exp-4 to 8 Hands on experience in IO block-level/full-module layout design Experience in developing IO's from scratch including floor-planning,Power bus design, ESD & PAD cell will be preferred. Hands on e...
Job Description: Memory Layout Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10...
Job Description: Analog Layout Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead. Candidate should have minimum 3+ years of hands-on experi...