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Keywords: Chip-Level Design Verification Engineer, Location: San Diego, CA

Page: 1

Enablement Engineer, On-chip power delivery, Staff

Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation... design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 13 Sep 2025

ASIC Design Verification Engineer (Security Group)

requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub... digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 08 Oct 2025

Sr. ASIC Design Verification Engineer, Amazon Leo

in system level verification using test benches constructed using UVM, System C and DPI-C · Develop a highly automated... connectivity. The Role: Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs...

Company: Amazon
Location: San Diego, CA
Posted Date: 22 Nov 2025

ASIC Design Verification Engineer, Amazon Leo

in system level verification using test benches constructed using UVM, System C and DPI-C · Develop a highly automated... connectivity. The Role: Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs...

Company: Amazon
Location: San Diego, CA
Posted Date: 15 Nov 2025

Staff/ Sr. Staff Design Verification Engineer - QGOV

skills & experience with assertion & coverage-based verification methodology Good understanding of chip-level functional... Summary: Design Verification Role: Familiarity with RTL design in Verilog and System Verilog Develop verification...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 18 Oct 2025

Senior Design Verification Engineer - QGOV

skills & experience with assertion & coverage-based verification methodology Good understanding of chip-level functional... Summary: Role: Familiarity with RTL design in Verilog and System Verilog Develop verification methodology, ensuring...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 18 Oct 2025
Salary: $115600 - 173400 per year

Sr. Verification Engineer - Mixed-Signal ICs

. Integrated Circuit (IC) Verification Engineer is responsible for developing and implementing verification plans for a variety... of mixed-signal integrated circuit blocks and systems. The Sr. Integrated Circuit (IC) Verification Engineer will closely...

Company: Semtech
Location: San Diego, CA
Posted Date: 02 Oct 2025
Salary: $130000 - 183206 per year

Senior Staff Formal Verification Engineer

& design verification. Support chip bring up and post silicon debug. Debug functional and timing models. Preferred... developing high-quality formal verification test benches to verify complex designs in GPU. Position involves working with design...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 03 Dec 2025

Emulation Verification Engineer

, you will be at the center of a chip design effort collaborating with all disciplines. Are you ready to help us deliver the... for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM. Minimum Qualifications...

Company: Apple
Location: San Diego, CA
Posted Date: 23 Oct 2025

Senior Analog Design Engineer

Senior Analog Design Engineer is responsible for designing, simulating and validating a variety of analog functions... such as ADCs, references, charge pumps, oscillators, pads. Ahead of detailed design, the Senior Analog Design Engineer...

Company: Semtech
Location: San Diego, CA
Posted Date: 23 Oct 2025
Salary: $130000 - 180000 per year

HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff (US Citizenship Required)

delivery of clean GDSII for tapeout, with full verification signoff. Perform full-chip and block-level static timing analysis... ** We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025

HW SOC/ASIC Physical Design Engineer, Senior (US Citizenship Required)

full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry... of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 19 Oct 2025
Salary: $115600 - 173400 per year

Sr. Embedded Firmware Design Engineer - Mixed-Signal ICs

. Embedded Firmware Design Engineer is responsible for designing, developing and validating a variety of firmware-based systems... and functions. Ahead of detailed design, the Sr. Embedded Firmware Design Engineer will actively participate in the definition...

Company: Semtech
Location: San Diego, CA
Posted Date: 02 Oct 2025
Salary: $130000 - 183206 per year

Sr. Digital IC Design Engineer

. Digital Integrated Circuit (IC) Design Engineer is responsible for designing, developing and validating a variety of digital... integrated circuit blocks and systems. Ahead of detailed design, the Sr. Digital IC Design Engineer will actively participate...

Company: Semtech
Location: San Diego, CA
Posted Date: 28 Sep 2025
Salary: $120000 - 183000 per year

Design Methodology Engineer

Summary: Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies... in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 20 Sep 2025

Principal Analog Design Engineer - Sensing Applications

Principle Analog Design Engineer is responsible for designing, simulating and validating a variety of analog functions... such as ADCs, references, charge pumps, oscillators, pads, etc. Ahead of detailed design, the Principle Analog Design Engineer...

Company: Semtech
Location: San Diego, CA
Posted Date: 10 Sep 2025
Salary: $140000 - 190000 per year

Staff SoC/RTL Design Engineer

responsibility of the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless... platform hardware and digital circuit component level and RF debugging. Responsibilities will include supporting design...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 20 Nov 2025
Salary: $152566 - 210000 per year

Senior ASIC Design Engineer, Amazon Leo

architecture in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level... and participate in System level verification using test benches constructed using UVM, System C and DPI-C · Ensure that the block...

Company: Amazon
Location: San Diego, CA
Posted Date: 19 Nov 2025

Wireless SoC Design Engineer

, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging... you to apply. Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements...

Company: Apple
Location: San Diego, CA
Posted Date: 31 Oct 2025

FE Design and Timing Engineer

, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment... products launched to delight millions of customers. Responsibilities Generate chip or block level static timing...

Company: Apple
Location: San Diego, CA
Posted Date: 25 Oct 2025