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Keywords: Chip-Level Design Verification Engineer, Location: San Diego, CA

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Design Verification Engineer

, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an industry-leading group of researchers... requirements and test cases for multiple state of the art IPs or SoCs. Design Verification Engineer Responsibilities Work...

Company: Meta
Posted Date: 26 Jun 2025

Wireless SOC Design Verification Engineer

. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group... RTL verification of block and top level SOC, comfortable with all areas of SOC Design Verification engineering...

Company: Apple
Location: San Diego, CA
Posted Date: 20 Jun 2025

Senior ASIC Design Verification Engineer (Security Group)

requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub... digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 13 Jun 2025

GNSS Design Verification Engineer

on every single Apple product? As a GNSS Design Verification Engineer, you will be responsible for pre-silicon RTL verification.... Description Build block/subsystem/chip level testbench using outstanding DV methodologies. Build verification plan from specification...

Company: Apple
Location: San Diego, CA
Posted Date: 29 May 2025
Salary: $115700 - 174200 per year

Wireless SOC Design Verification Engineer

architecture, etc. Description As a Design Verification Engineer on our team, you'll be at the center of the verification...! This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, being comfortable...

Company: Apple
Location: San Diego, CA
Posted Date: 29 May 2025

Design Verification Engineer

Perl scripts to process results. Modify design specs by conducting test plan reviews. Develop block or full chip tests... and triage failures. Drive the verification efforts in the specific area. Support gate level functional verification, run...

Company: Apple
Location: San Diego, CA
Posted Date: 29 Jun 2025
Salary: $135400 - 204000 per year

SoC Physical Design Verification Engineer

, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC... of a critical team responsible for physical verification of an SOC. Description - As a member of our physical design team...

Company: Apple
Location: San Diego, CA
Posted Date: 06 Jun 2025
Salary: $115700 - 174200 per year

SoC Physical Design Verification Engineer

, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC... of a critical team responsible for physical verification of an SOC. Description - As a member of our physical design team...

Company: Apple
Location: San Diego, CA
Posted Date: 06 Jun 2025

Enablement Engineer, On-chip power delivery, Staff

Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation... design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 24 May 2025

ASIC Design & Integration Engineer

, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced... and maintain methodology and flow checks for your design. Interact with our verification team to ensure appropriate validation...

Company: Apple
Location: San Diego, CA
Posted Date: 05 Jul 2025

Sr. ASIC Modem Design Engineer, Project Kuiper

hiring a Sr. Modem Design Engineer within a high performance ASIC design team. This team is using industry leading... specification to RTL to optimizing timing / power to chip level validation. · Develop solutions optimizing customer experience...

Company: Amazon
Location: San Diego, CA
Posted Date: 04 Jul 2025
Salary: $143300 - 247600 per year

Design Methodology Engineer

Summary: Qualcomm's Design Technology team is seeking a motivated engineer to drive development of advanced methodologies... in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 03 Jul 2025
Salary: $115600 - 173400 per year

ASIC Design & Integration Engineer

, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced... and maintain methodology and flow checks for your design. Interact with our verification team to ensure appropriate validation...

Company: Apple
Location: San Diego, CA
Posted Date: 03 Jul 2025

SoC Physical Design Engineer, Electrical Analysis

and verification of an SoC. Description - As a senior member of our SoC physical design team, you will be performing various... electrical analyses at the block or chip level, including but not limited to: Gridcheck, ESD, Static/Dynamic IR, EM, Noise...

Company: Apple
Location: San Diego, CA
Posted Date: 26 Jun 2025

SoC Physical Design Engineer, Electrical Analysis

and verification of an SoC. Description - As a member of our physical design team, you will be performing various electrical... analyses at the block or chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM. - You will work...

Company: Apple
Location: San Diego, CA
Posted Date: 18 Jun 2025

Memory Controller Design Engineer

, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will also participate in C/C... for all. QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 13 Jun 2025
Salary: $98500 - 147700 per year

CPU Physical Design – Low Power Signoff Engineer

of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work... Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 08 Jun 2025

Design Methodology Engineer

Engineering General Summary: Qualcomm’s Design Technology team is seeking a motivated engineer to drive development... of advanced methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 03 May 2025

LPDDR PHY System Design Engineer

of design-for-yield principles and production-level challenges specific to DDR systems. Preferred Qualifications Exposure..., Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience...

Company: Qualcomm
Location: San Diego, CA
Posted Date: 03 Jul 2025

System Design Engineer

design of Power Delivery Networks (PDNs) and high-speed signals at PCB level Familiar with Cadence APD/Allegro for physical... design Familiar with High Density Interconnect (HDI) PCB and Flip-Chip (FC) BGA package substrate technologies Ability...

Company: Apple
Location: San Diego, CA
Posted Date: 20 Jun 2025