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Keywords: Design Verification Methodology Engineer - (UVM/SV), Location: Santa Clara, CA

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Senior ASIC Verification Engineer, Coherent High Speed Interconnect

. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent...'s from scratch using SV and UVM methodology is desired. C++ programming language experience, scripting ability and an expertise...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Aug 2025

Emulation Engineer II

Specific integrated circuit (ASIC)/ System on Chip (SoC) emulation verification with System Verilog (SV)/Universal Verification... Methodology (UVM) environments using any Standard Emulator (Palladium, Protium) 2+ years experience with Python or Perl scripting...

Company: Microsoft
Location: Santa Clara, CA
Posted Date: 08 Oct 2025