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Keywords: Digital Design (RTL) Engineer, Location: Santa Clara, CA

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CPU DFT Verification Engineer

. Description Description As a DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL designers... Experience with digital logic design, test/debug feature, or DFT architecture Experience with DFT and structural debug concepts...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Nov 2024

CPU DFT Verification Engineer

. Description Description As a DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL designers... Minimum BS Computer architecture knowledge Digital design knowledge including using Verilog for digital design Key...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Nov 2024
Salary: $121900 - 183600 per year

CPU Processor Power Management Verification Engineer

, or power management architecture Experience with digital design verification including knowledge of Verilog/System-Verilog...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 08 Nov 2024

Staff IP CAD Engineer

is located at on-site at our Santa Clara Design Center. As a member of the IP Infrastructure Team, you will share.... Proficient in IP model formats such as SPICE, LEF, GDS, LIB, etc. Knowledgeable about IP quality requirements for ASIC design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 25 Jan 2025
Salary: $93720 - 140400 per year

Power Methodology and Modeling Engineer - New College Grad 2024

++. Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities. Understanding of VLSI, digital design..., and low power design. Basic understanding of chip design process from RTL design to tape-out. Background in machine...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 06 Nov 2024

Graphics FE Implementation Engineer

will be responsible for RTL to netlist generation working collaboratively with the RTL and Physical design teams. You will also deliver... Minimum Qualifications Relevant Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design Experience...

Company: Apple
Location: Santa Clara, CA
Posted Date: 03 Nov 2024
Salary: $121900 - 183600 per year