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Keywords: Low Power Design Engineer, Location: Tijuana, B.C.

Page: 1

Design for test Engineer

implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low-power, multi-voltage...Descripción Our Digital ASIC Design Team is currently seeking candidates who will be responsible for the...

Company: NAPS
Location: Tijuana, B.C.
Posted Date: 11 Dec 2024

DFT CAD Engineer

, Synopsys or equivalent Deep understanding of SoC design, low power, timing exceptions and complex clock structures... Collaborate with SoC design, product and test engineer teams to drive standardization of DFT/ATPG methodology and flow across the...

Company: NAPS
Location: Tijuana, B.C.
Posted Date: 07 Dec 2024