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Keywords: Power UPF Methodology Engineer, Location: Cupertino, CA

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Power UPF Methodology Engineer

design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF... Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs...

Company: Apple
Location: Cupertino, CA
Posted Date: 28 Jun 2025

Physical Synthesis CAD Engineer

Experience in CAD flow or FE methodology development Experience with Low Power implementation flows (UPF) is a plus Experience... power checks (UPF) or place and route tools is a plus Proficiency with TCL, Python or Perl scripting languages strongly...

Company: Apple
Location: Cupertino, CA
Posted Date: 31 Jul 2025

Physical Synthesis CAD Engineer

is a plus Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus Proficiency with TCL..., power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently...

Company: Apple
Location: Cupertino, CA
Posted Date: 31 Jul 2025