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Keywords: Power UPF Methodology Engineer, Location: Cupertino, CA

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Power UPF Methodology Engineer

design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF... Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs...

Company: Apple
Location: Cupertino, CA
Posted Date: 28 Jun 2025

Design Verification Engineer

. Experience with power-aware (UPF) or similar verification methodology. Excellent knowledge of one of the scripting languages... engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming...

Company: Apple
Location: Cupertino, CA
Posted Date: 20 May 2025

ASIC Design Engineer - Pixel IP

including UPF power intent specification. Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB). Industry..., you'll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Apr 2025

ASIC Design Engineer - Pixel IP

including UPF power intent specification. Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB). Industry..., you'll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple...

Company: Apple
Location: Cupertino, CA
Posted Date: 23 Apr 2025

Digital Design Engineer

and design. Industry low power methodologies including UPF/CPF and low power check techniques. High speed interface design... the complete design collaterals. Design, implement, and debug complex logic designs to optimize performance, power...

Company: Apple
Location: Cupertino, CA
Posted Date: 29 Jun 2025
Salary: $143100 - 214500 per year

Physical Synthesis CAD Engineer

Experience in CAD flow or FE methodology development Experience with Low Power implementation flows (UPF) is a plus Experience... power checks (UPF) or place and route tools is a plus Proficiency with TCL, Python or Perl scripting languages strongly...

Company: Apple
Location: Cupertino, CA
Posted Date: 30 Apr 2025

Physical Synthesis CAD Engineer

is a plus Experience in linting, static timing analysis, low power checks (UPF) or place and route tools is a plus Proficiency with TCL..., power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently...

Company: Apple
Location: Cupertino, CA
Posted Date: 30 Apr 2025