Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: RTL Engineer, Location: Bangalore, Karnataka

Page: 9

Digital Design Verification Engineer

. - Hand on experience in RTL and Gate level simulations of complex ASIC at block and top level - Expert in using simulation... at all phases (RTL, GLS), - Understanding spec and coming up with testplan. Writing TB components, testcases, checkers, assertions...

Posted Date: 01 Dec 2024

Senior Digital Design Engineer

at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence... catalog of digital IPs to enable ease of information sharing to customers across different BUs Develop User Guides for RTL...

Posted Date: 19 Nov 2024

Associate III - VLSI IO/ACD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 09 Feb 2025

Associate II - VLSI IO

work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks... from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes...

Company: UST
Posted Date: 09 Feb 2025

Technical Lead I - VLSI GCAD Lead

Backend or Analog design with minimal supervision Outcomes: * Work as an individual contributor owning any one task of RTL...: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus...

Company: UST
Posted Date: 09 Feb 2025

Associate III - VLSI GCAD

of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA... Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS...

Company: UST
Posted Date: 08 Feb 2025

Sr. Manager Silicon Design Engineering

_ SENIOR MANAGER SILICON DESIGN ENGINEER THE ROLE: The ideal candidate will get to work on Verification of complex Analog... RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed...

Posted Date: 08 Feb 2025

Architect Digital Design

-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large variety... of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...

Company: onsemi
Posted Date: 06 Feb 2025

Architect Digital Design

and analog/mixed-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large... variety of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...

Company: onsemi
Posted Date: 06 Feb 2025

ASIC Design Engr 2

Job Description: FPGA Verification Engineer We are looking for experienced FPGA Verification Engineer. As a FPGA... Verification Engineer at Infinera you will work for a high complexity DWDM equipment for LH/ULH applications. You will work...

Company: Infinera
Posted Date: 04 Feb 2025

DRAM Verification - Memory Team

Position Summary DRAM Verification Role and Responsibilities Role : Looking for Design verification Engineer... : Looking for Design verification Engineer with 7+ years of experience Responsibilities : · Architect and Develop IP level/System Level...

Company: 삼성전자
Posted Date: 21 Jan 2025

Design Verification Lead/Manager - CPU Team - 10-15yrs

_ Lead / Manager - CPU Performance Verification Engineer THE ROLE: The person will be part of AMD's CPU Performance... pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team...

Posted Date: 17 Jan 2025

Associate II - VLSI AL CAD

work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks... from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes...

Company: UST
Posted Date: 09 Jan 2025

Frontend CAD Developer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.../Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design...

Company: Qualcomm
Posted Date: 04 Jan 2025

Full chip SoC timing lead

_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Physical Design... and problem-solving skills. Should have hands on Physical Design experience and must have handled RTL to GDS II at Top level...

Posted Date: 28 Dec 2024

ASIC Design Engr 2

networks that generate billions in service revenue for our customers. Title: ASIC Physical Design Engineer Location: India... cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies...

Company: Infinera
Posted Date: 21 Dec 2024

Frontend CAD Developer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical.../Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design...

Company: Qualcomm
Posted Date: 19 Dec 2024

WEE - ER

Family GoLang Data Engineer Java Full Stack (React) Java Full Stack (Angular) .Net Full Stack (React) Java FS DotNet... Cell Physical Design DFT RTL Design & Verification Android Framework C++ Developer (QT/QML) Autosar Java Selenium...

Company: Wipro
Posted Date: 18 Dec 2024

PE Verification Engineering

Verification Engineer to join our PCIe Express IP Products team in Bangaluru, India. The successful candidate will participate... in pre-silicon RTL Verification activities related to PCIe Controller SoftIP development, on leading-edge PCI-Express and CXL...

Company: Rambus
Posted Date: 04 Dec 2024

SOC Implementation Lead with 13+ years experience(SMTS )

_ SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow from floor... synthesis (CTS), routing, and optimization to meet PPA goals. Work closely with RTL, DFT and IP teams to ensure seamless...

Posted Date: 20 Nov 2024