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Keywords: SOC Full Chip Timing Engineer, Location: Bangalore, Karnataka

Page: 1

SOC Full Chip Timing Engineer

and methodologies such as STA, Synthesis, Clocking is required. Good understanding and exposure of overall Timing closure cycle in SoC... of STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited...

Company: Intel
Posted Date: 25 Mar 2025

Full-Chip Floor planning Lead (SMTS Silicon Design Engineer)

_ SMTS SILICON DESIGN ENGINEER As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design... groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement...

Posted Date: 01 Mar 2025

Principal Engineer, Physical Design Timing

in SoC and ASIC design flows on taped out designs 5. Expertise in timing closure at block/chip level and ECO flows 6.... Experience with scripting in an interpreted language Preferred Qualifications: 1. Experience with full chip integration...

Company: Intel
Posted Date: 22 Mar 2025

SOC Design Engineer/Lead

for a CPU required to generate cell libraries, functional units, and the AI SOC / CPU IP block for integration in full chip... designs. Participates actively in the definition of architecture and microarchitecture features of the AI SOC/CPU being...

Company: Intel
Posted Date: 24 Mar 2025

GPU SOC Design Engineer

GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture... to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation...

Company: Intel
Posted Date: 19 Feb 2025

ASIC Design Engineer

full-chip and subsystem timing working with synthesis and static timing analysis teams. Experience with DFT tools for scan... of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers...

Company: Amazon
Posted Date: 29 Mar 2025

Principal GPU RTL Design Engineer

GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture... correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. As a principal engineer...

Company: Intel
Posted Date: 28 Mar 2025

Physical Design (MTS Silicon Design Engineer)

_ MTS SILICON DESIGN ENGINEER THE ROLE: As the SoC Subsystem Physical Design Lead, you will lead the physical design... physical design issues that impact overall system performance. Collaborate with the Full Chip physical verification team...

Posted Date: 19 Mar 2025

Lead Engineer - RTL Design, Front End

Title: Lead Engineer - RTL Design, Front End About GlobalFoundries GlobalFoundries is a leading full-service.... For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Test Chip Architect...

Posted Date: 06 Mar 2025

ASIC Engineer, Physical Design

to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, Physical Design Responsibilities.... Programming/scripting skills: TCL, Python, Perl or Shell. Preferred Qualifications Experience in full chip floor planning...

Company: Meta
Posted Date: 04 Feb 2025

Senior Design Engineer

for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs... strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing...

Company: Intel
Posted Date: 27 Mar 2025

DFT Engineer

units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture..., including timing, routing, placement or clocking analysis SOC architecture, RTL coding and post silicon debug. Experience...

Company: Intel
Posted Date: 27 Mar 2025

Principal Engineer, RTL ASIC Design

on Full Chip Integration of Complex SoC design. Has worked on complex chips such as network processors, CPUs ,GPUs ,NOCs... verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip...

Company: Marvell
Posted Date: 23 Mar 2025

Principal Engineer, Design Verification

and deliver on design verification of complex Intellectual Property (IP) or Subsystem or complete full chip (SoC) level features... implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC...

Posted Date: 19 Mar 2025

Experienced Logic Design Engineer

for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs... strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing...

Company: Intel
Posted Date: 13 Mar 2025

Physical Design Engineer - Foundry Team

physical design and timing closure of complex blocks and full-chip designs. Experience in top level floor planning including... . * Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking...

Company: Samsung
Posted Date: 05 Mar 2025

Principal Engineer, RTL ASIC Design

on Full Chip Integration of Complex SoC design. Has worked on complex chips such as network processors, CPUs ,GPUs ,NOCs... analysis, full-chip simulation and emulation, performance and power analysis and debug Help develop and/or evaluate design...

Company: Marvell
Posted Date: 12 Feb 2025