Job Role: Senior Mixed Signal DV Engineer Job Location: San Jose CA Job description: We are seeking Mixed Signal...-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital...
segments of the Semiconductor industry, including AI. Our ASIC products division is looking for a senior engineer to guide... to have: Exposure to SERDES communications protocols. Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end...