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Keywords: Test Timing Engineer, Location: San Jose, CA

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Test Timing Engineer

, developing and testing some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing... Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 08 Nov 2024

Timing Constraint Engineer

You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints.... Experience with block/full chip SDC development in functional and test modes. Experience in Static Timing Analysis and prior...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 14 Nov 2024

ASIC Design Technical Leader - Design & Timing Constraints Focus

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock..., you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 12 Dec 2024

Calibration/Diagnostics Engineer (Nextest, San Jose)

We are the global test and automation specialists, powering next-generation technologies through sophisticated... solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time...

Company: Teradyne
Location: San Jose, CA
Posted Date: 01 Jan 2025

Principal Silicon Validation and Verification Engineer

I/O. Bench test debug and validation of clock generation and timing IPs, data converters, TIAs, modulator drivers, clock and data...Broadcom is looking for a principal silicon validation and verification engineer. In this highly visible role...

Company: Broadcom
Location: San Jose, CA
Posted Date: 26 Dec 2024

Calibration/Diagnostics Engineer (Nextest, San Jose)

We are the global test and automation specialists, powering next-generation technologies through sophisticated... solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time...

Company: Teradyne
Location: San Jose, CA
Posted Date: 21 Dec 2024

IC Design Engineer

Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture... team on test plan development, debugging, and coverage closure Collaborate with physical design team on constraint...

Company: Broadcom
Location: San Jose, CA
Posted Date: 15 Dec 2024
Salary: $119000 - 190000 per year

DFT Engineer

for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT... architecture, to implementation, verification, timing closure, ATE pattern bringup. . You will also drive/push state of the art...

Company: Broadcom
Location: San Jose, CA
Posted Date: 11 Dec 2024
Salary: $119000 - 190000 per year

R&D Engineer Physical Design

synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure...Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines including...

Company: Broadcom
Location: San Jose, CA
Posted Date: 31 Oct 2024
Salary: $119000 - 190000 per year

R&D Engineer

R&D Staff Engineer The ideal candidate will have expertise in integrated-circuit process technologies... fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure...

Company: Broadcom
Location: San Jose, CA
Posted Date: 30 Oct 2024
Salary: $107000 - 190000 per year

Digital Design Engineer

engineers and physical design teams to ensure functional correctness, timing closure, and overall design robustness... and refine micro-architecture specifications, focusing on efficient and robust design implementations. Synthesis and Timing...

Company: Broadcom
Location: San Jose, CA
Posted Date: 19 Dec 2024
Salary: $119000 - 190000 per year

Mixed Signal Design Engineer

and architecture technical specifications, AMS pre-silicon verification, AMS post-silicon characterization/validation test plans... on test-plans and characterization reports PREFERRED EXPERIENCE: Strong fundamentals and knowledge of mixed signal...

Posted Date: 13 Dec 2024

ASIC Design Engineer

to understand chip architecture, implement and get it verified. You will work closely with Back-end team on timing signoff...-architecture specifications and participate in specification and test plan reviews. Architect and implement complex RTL designs...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 05 Dec 2024
Salary: $133300 - 186800 per year

RTL Design SOC Integration Engineer

and complexity Own the design and implementation of blocks to meet functional, timing, area, and power requirements Guide... and review verification for these blocks Design and implement logic functions that enable efficient test and debug Implement...

Posted Date: 15 Nov 2024

Senior ASIC Design Engineer

- Lint, CDC, RDC and others Timing closure - synthesis, logic-depth reduction, timing constraints Design area optimization... Physical Design interfacing Sub-system and IP Integration into SoC Feature specification and implementation Test case debug...

Posted Date: 14 Nov 2024

NPU HW Power and Performance (Principal Engineer)

and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance...

Posted Date: 13 Nov 2024