As a UVM/ SystemVerilog Design Verification Engineer, you will own functional verification for a custom controller... of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining...
Job Description: As an FPGA design engineer, you will take ownership of project components and develop scalable RTL... Design Microarchitecture FPGA design tools (Vivado or Quartus Prime) for synthesis Verification and Validation Debugging...