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Keywords: ASIC Physical Design , Location: Bangalore, Karnataka

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ASIC Physical Design Tools Flows & Methodology Lead

_ MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM.../Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless...

Posted Date: 11 Apr 2025

Sr. Silicon Design Engineer (AECG ASIC Physical Design)

_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PHYSICAL DESIGN) THE ROLE: The focus of this role in the AECG ASIC organization... and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL...

Posted Date: 11 Apr 2025

ASIC Physical Design & Implementation Lead

_ SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design & Implementation) THE ROLE: The focus of this role in the AECG... ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer...

Posted Date: 11 Apr 2025

Sr. Silicon Design Engineer (AECG ASIC Physical verification Engineer)

of the physical integration and verification team , you will work closely with the physical design implementation, IP teams... on FC SoC physical integration, Tile Physical verification and tapeout with physical design engineers. The candidate...

Posted Date: 11 Apr 2025

ASIC Engineer, Physical Design

Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. Physical Design Engineers... to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, Physical Design Responsibilities...

Company: Meta
Posted Date: 04 Feb 2025

Sr. Silicon Design Engineer (AECG ASIC STA)

_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC STA) THE ROLE: We are looking for an adaptive, self-motivative timing engineer... highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages...

Posted Date: 16 Apr 2025

ASIC Design Engineer - Design & Timing Constraints | 8+ years

constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking... chips. Responsibilities include: Being a member of design team who oversees fullchip SDCs and works with physical design...

Company: Cisco Systems
Posted Date: 15 Apr 2025

Principal Engineer, RTL ASIC Design

coding with System Verilog assertions Well-versed in all stages of the ASIC design flow (including specification..., from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect...

Company: Marvell
Posted Date: 23 Mar 2025

ASIC Design and STA Engineer

-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence... Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) Hands on STA experience from early stages...

Company: Nvidia
Posted Date: 20 Feb 2025

ASIC Design Engineer :: RTL Design | Verilog or System Verilog | Exp - 7+ Years

with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close...'s Degree in Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System...

Company: Cisco Systems
Posted Date: 19 Feb 2025

ASIC DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various... for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the...

Company: Cisco Systems
Posted Date: 08 Apr 2025

ASIC Flow Methodology Lead

in ASIC PDK kit/Physical design/ ASIC Design automation role. Hands-on experience with Synopsys and Cadence Place and Route... documents for ASIC flows and PDK. Train the users and design engineers on ASIC flows and tech file usage. Debug the complex...

Company: Intel
Posted Date: 24 Apr 2025

ASIC DV Engineer, PCIe Verification

closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design...Meta is hiring ASIC Verification Engineer with in-depth understanding of PCIe Express within the Infrastructure...

Company: Meta
Posted Date: 03 Apr 2025

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years

Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical... through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff...

Company: Cisco Systems
Posted Date: 29 Mar 2025

ASIC Engineer, Implementation

or location. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization... in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback...

Company: Meta
Posted Date: 22 Mar 2025

ASIC Engineer, Front-End Implementation

, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them... with RTL Synthesis and design optimization for Power, Performance, Area. Knowledge of front-end and back-end ASIC tools...

Company: Meta
Posted Date: 13 Feb 2025

ASIC Frontend Implementation, CDC/RDC

with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical... Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using...

Company: Meta
Posted Date: 08 Feb 2025

Asic Engineer, EDA Infrastructure

, efficiency and maintenance Work with internal infrastructure team on adapting Meta infrastructure to ASIC design solutions... development and support Physical Design implementation flow development and support Minimum Qualifications Knowledge...

Company: Meta
Posted Date: 03 Feb 2025

Physical Design Engineer

Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies.... Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 6-11 years of experience in physical design from product...

Company: Qualcomm
Posted Date: 23 Apr 2025

Physical Design Engineer

Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies.... Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 6-11 years of experience in physical design from product...

Company: Qualcomm
Posted Date: 12 Apr 2025