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Keywords: Advanced Package Layout Design Engineer, Staff, Location: Santa Clara, CA

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Advanced Package Layout Design Engineer, Staff

is seeking a talented High-speed IC package layout design engineer to contribute to the development of advanced microelectronic... packages for semiconductors supporting up to 224 Gb/s data rates. The engineer will be responsible for package layout including...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Mar 2025
Salary: $105470 - 158000 per year

Staff Engineer, Analog Layout

Custom Layout Engineer to contribute to the development of high-speed connectivity, broadband analog, and data transport... and timelines Responsible for floor planning, custom layout, and verifying compliance with design rules and schematics, including...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 18 Apr 2025
Salary: $100210 - 150100 per year

Senior Staff Analog Mixed Signal IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Principal... Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 21 Feb 2025
Salary: $140350 - 210200 per year

Analog Design, Senior Staff Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog Design Engineer... of innovation in the field of High Speed SerDes Links. What You Can Expect As an analog circuit design engineer...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 02 Feb 2025
Salary: $128160 - 192000 per year

Analog IC Design Engineer, Senior Staff

, etc.). Familiarity with CDR architectures and implementations. Design experience in advanced CMOS technologies, design with FinFet...-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Apr 2025
Salary: $140350 - 210200 per year

Analog IC Design Engineer, Staff

, counters, dividers, etc.) Familiarity with CDR architectures and implementations Design experience in advanced CMOS... budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Apr 2025
Salary: $118900 - 178100 per year

Senior Staff Analog Mixed-Signal Design Engineer

. What You Can Expect Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies..., CTLE, VGA, and TX Drivers. Supervise and guide layout activities to ensure design accuracy and performance. Conduct post...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 08 Feb 2025
Salary: $140350 - 210200 per year

Application Engineering Staff Engineer

flow, including design, layout, simulation, and timing analysis, to identify potential issues and weaknesses in designs... understanding of various aspects of ASIC design flow, including design, layout, simulation, and timing analysis, to identify...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 27 Feb 2025
Salary: $102880 - 154100 per year