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Keywords: CAD Engineer - Timing for Gate-Level Flows & Methodologies, Location: Sunnyvale, CA

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CAD Engineer - Timing for Gate-Level Flows & Methodologies

timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams..., you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 10 Apr 2025

CAD Engineer - Timing for Gate-Level Flows & Methodologies

timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams..., you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 10 Apr 2025

CAD Gate-level 3DIC EM/IR Engineer

-on experience in power EM/IR analysis to develop, define and refine the methodologies and flows for gate-level, as well...! As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands...

Company: Apple
Location: Sunnyvale, CA
Posted Date: 12 Feb 2025
Salary: $121900 - 183600 per year