Find your dream job now!

Click on Location links to filter by Job Title & Location.
Click on Company links to filter by Company & Location.
For exact match, enclose search terms in "double quotes".

Keywords: CPU Design Timing Engineer, Location: Santa Clara, CA

Page: 1

CPU Design Timing Engineer

. Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include... to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Timing Engineer

. Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include... to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Top-Level Design Verification Engineer

Top-Level Design Verification Engineer owning the verification methodology, tools, and flow of a high performance lower... next groundbreaking Apple product. In this highly visible role, you will be at the center of a chip design effort interfacing with many...

Company: Apple
Location: Santa Clara, CA
Posted Date: 18 Sep 2025
Salary: $126800 - 190900 per year

CPU Top-Level Design Verification Engineer

Top-Level Design Verification Engineer owning the verification methodology, tools, and flow of a high performance lower... with understanding of timing closure, area optimization, and power-aware design techniques SystemVerilog - Proficiency in SystemVerilog...

Company: Apple
Location: Santa Clara, CA
Posted Date: 18 Sep 2025

CPU Micro-architect/RTL Designer

Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture... specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 24 Sep 2025

CPU Power Management Microarchitect/RTL Engineer

, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power... management solutions. Description As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2025

CPU Cache Microarchitect/RTL Engineer

specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing...-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability...

Company: Apple
Location: Santa Clara, CA
Posted Date: 30 Oct 2025

CPU Gate Level Synthesis Engineer

groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level... CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU ML Microarchitect/RTL Engineer

• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU front-end... and/or out-of-order subsystem for our performant cores. Description As a CPU Microarchitect/RTL Engineer, you will own...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU ML Microarchitect/RTL Engineer

• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer..., floating-point, and/or load/store execution for our performant cores. Description As a CPU Microarchitect/RTL Engineer...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer..., floating-point, and/or load/store execution for our performant cores. Description As a CPU Microarchitect/RTL Engineer...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer

ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Oct 2025
Salary: $126800 - 190900 per year

RISCV CPU Systems Architecture/RTL Engineer – Senior Level

understanding of logic design principles, including timing and power implications Preferred Qualifications Master's degree... microarchitecture techniques Knowledge of high-performance design strategies and trade-offs in CPU microarchitecture Experience...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

CPU Integration CAD Engineer

cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop... of other Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 04 Oct 2025

CPU RTL LLC Engineer

targeted for high performance, low power devices in the cache and memory controller design. As a CPU Micro-architecture and RTL... Design Engineer, you will work with chip architects to conceive of the micro-architecture and also help with architecture...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 16 Sep 2025

Senior ASIC Design Engineer – Clocks IP

ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team... the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Senior Logic Design Engineer– Physical Design

We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design... Team, you will be responsible for the design of CPU on-chip interconnect network and last-level caches, working closely...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Sep 2025

Senior Circuit Design Engineer - Power Modeling and Simulation

as a leader in this next wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling... in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly motivated individual who...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 30 Aug 2025