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Keywords: CPU Design Timing Engineer, Location: Santa Clara, CA

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CPU Design Timing Engineer

. Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include... to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Design Timing Engineer

. Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include... to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Physical Design Methodology and Optimization Engineer

with CPU, CAD, and design teams to engineer new flows/algorithms to improve PPA • Detailed analysis across partitions... groundbreaking Apple products! In this highly visible role as a part of an industry-recognized and innovative CPU design team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

CPU Physical Design Engineer

design. Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS... and optimizations and their adoption in CPU design • Will work with x-functional top-level teams on the aspects of CPU floorplan, timing...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

CPU Physical Design Methodology and Optimization Engineer

with CPU, CAD, and design teams to engineer new flows/algorithms to improve PPA • Detailed analysis across partitions... groundbreaking Apple products! In this highly visible role as a part of an industry-recognized and innovative CPU design team...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

CPU Implementation Engineer

implementation. Description As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro... on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design • Work with x-functional top...

Company: Apple
Location: Santa Clara, CA
Posted Date: 06 Nov 2025

CPU Power Management Microarchitect/RTL Engineer

, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power... management solutions. Description As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2025

CPU Cache Microarchitect/RTL Engineer

specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing...-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability...

Company: Apple
Location: Santa Clara, CA
Posted Date: 31 Oct 2025

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer..., floating-point, and/or load/store execution for our performant cores. Description As a CPU Microarchitect/RTL Engineer...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU ML Microarchitect/RTL Engineer

• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer - Execution, Load/Store

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer..., floating-point, and/or load/store execution for our performant cores. Description As a CPU Microarchitect/RTL Engineer...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU ML Microarchitect/RTL Engineer

• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Gate Level Synthesis Engineer

groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level... CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU front-end... and/or out-of-order subsystem for our performant cores. Description As a CPU Microarchitect/RTL Engineer, you will own...

Company: Apple
Location: Santa Clara, CA
Posted Date: 28 Oct 2025

CPU Microarchitect/RTL Engineer

ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals... engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Oct 2025
Salary: $126800 - 190900 per year

RISCV CPU Systems Architecture/RTL Engineer – Senior Level

understanding of logic design principles, including timing and power implications Preferred Qualifications Master's degree... microarchitecture techniques Knowledge of high-performance design strategies and trade-offs in CPU microarchitecture Experience...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 15 Oct 2025

CPU Integration CAD Engineer

cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop... of other Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 04 Oct 2025

ASIC Design Engineer, GPU/ML Shader Core

your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status... for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean...

Posted Date: 19 Dec 2025

Circuit Design Engineer, Power Modeling and Simulation - New College Grad 2026

as a leader in this next wave of computing. We are now looking for a motivated Circuit Design Engineer in Power Modeling... in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly motivated individual who...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 19 Dec 2025
Salary: $108000 - 184000 per year

ASIC Clocks Design Engineer - New College Grad 2025

ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team... the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 11 Dec 2025
Salary: $108000 - 184000 per year