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Keywords: Design Engineer - Memory Subsystem, Location: Bangalore, Karnataka

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Senior Design Engineer - Memory Subsystem

. Expertise in Verilog. Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP... on the design of state of the art memory sub-system components used in their industry-leading GPUs and SOCs. This position...

Company: Nvidia
Posted Date: 23 Oct 2025

DV Engineer / Senior Engineer – PCIE/CXL Subsystem Verification

We are looking for passionate and motivated PCIE Gen6/CXL 3.0 IP/Subsystem Design Verification Engineers to work on PCIE/CXL based Memory Pooling...

Company: Quest Global
Posted Date: 24 Sep 2025

Lead Design Engineer

on Microcontrollers. Responsible for collaborating with hardware designers and memory subsystem architects to derive training.... Job Description Be part of the Cadence DDR PHY IP Front End Design team responsible for - Develop firmware for DDR5 PHY using...

Posted Date: 12 Oct 2025

Principal Engineer, ASIC Development Engineering (RTL Design)

development, with a proven track record of leading complex project At hands on in IP / blocks / subsystem complex design... in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living...

Company: SanDisk
Posted Date: 25 Nov 2025

Senior ASIC Design Engineer - XBAR IP

working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors.... Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging...

Company: Nvidia
Posted Date: 11 Nov 2025

Senior ASIC Design Engineer - NOC IP

working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors.... Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging...

Company: Nvidia
Posted Date: 14 Sep 2025

Lead Software System Design Eng

your career. LEAD SOFTWARE SYSTEM DESIGN ENGINEER THE ROLE: The right engineer will drive the success of power IP..., and able to independently drive tasks to completion PREFERRED EXPERIENCE: Own memory subsystem bring-up including DDR...

Posted Date: 15 Nov 2025

Principal Product Engineer

EngineerMemory IP Products Join a growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY... Help with internal system integration and QA testing of Memory subsystem products (Controller + PHY) Analyze and resolve...

Posted Date: 23 Oct 2025

CPU Performance & Power Analyst - Principal Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same...

Company: Qualcomm
Posted Date: 06 Dec 2025

SOC Verification Engineer: Graphics DV

your career. SDE/MTS/SMTS SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: Graphics DV ): Work on SOC level... common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows...

Posted Date: 28 Nov 2025

PLATFORM EMULATION ENGINEER

your career. MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, execute the verification..., GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools Good understanding...

Posted Date: 27 Nov 2025

PLATFORM EMULATIION ENGINEER

, GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools Good understanding... your career. PLATFORM EMULATIION ENGINEER: THE ROLE: We are looking for an adaptive, self-motivative platform emulation...

Posted Date: 27 Nov 2025

LEAD PLATFORM EMULATION ENGINEER

, GPU, and Memory subsystem Proficient in debugging firmware and RTL code using simulation tools Good understanding... your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification...

Posted Date: 27 Nov 2025

CPU Performance & Power Analyst/Staff Engineer

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... and performance team. Responsible for analyzing the performance aspects of Snapdragon CPU subsystem and influence the same...

Company: Qualcomm
Posted Date: 22 Nov 2025

Senior DFT Engineer, SSG

. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning... leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner...

Company: Amazon
Posted Date: 25 Oct 2025

CIMWare - Principal Engineer _CTO's Office

events. Job Description of a Principal EngineerDesign, implement, and maintain PCIe device drivers for the Linux kernel...Company - CIMWare Principal Engineer – CTO's Office Work Mode- 5 Days Onsite Introduction :- CIMware is an equal...

Company: Nexthire
Posted Date: 11 Sep 2025

Sr. SOC level verification -GDP (PCIE,USB,Ethernet ) Engineer

_ SENIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: GDP DV ): Work on SOC level verification activities... some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows...

Posted Date: 09 Sep 2025

Embedded Dev (QNX)- Engineer, Senior

, the candidate will be responsible for any automation of design under test along with validation efforts and working... closely with design/production/bench IP teams. Minimum Qualifications: • Bachelor's degree in Engineering, Information...

Company: Qualcomm
Posted Date: 28 Nov 2025

Staff Engineer – NSP/NPU System Software

, design, and development of system software to use SoCs extensive heterogeneous computing capabilities to allow running... working on design, development, integrate, commercialize and maintenance of system software for CPU, NSP processors...

Company: Qualcomm
Posted Date: 01 Nov 2025

Senior engineer

according to the SOC design specification, requirements, and usage model – at subsystem and chip level Hands-on and Experienced... in typical embedded sub-systems (processor (ARC / Xtensa / ARM etc, system fabrics, DSP functions, memory, USB, communication...

Company: Varite
Posted Date: 03 Oct 2025