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Keywords: Emulation and Silicon Validation Engineer, Location: San Jose, CA

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Emulation and Silicon Validation Engineer

features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify... design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize...

Company: Broadcom
Location: San Jose, CA
Posted Date: 28 Nov 2024
Salary: $119000 - 190000 per year

Emulation and Silicon Validation Engineer

features in both emulation phase and post-silicon Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify... design blocks, libraries, and verification components to streamline emulation processes. Silicon Bring-up: Plan, organize...

Company: Broadcom
Location: San Jose, CA
Posted Date: 28 Nov 2024
Salary: $119000 - 190000 per year

Senior Staff Emulation Engineer - ZEBU

, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup...: What you’ll be doing: The Emulation engineer will be responsible for validation of Emulation product (ZeBu) and various solutions...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Senior Staff Emulation Engineer - ZEBU

, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup... What you’ll be doing: The Emulation engineer will be responsible for validation of Emulation product (ZeBu) and various solutions...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

Sr. Emulation Engineer - HAPS

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation.... Embedded services: device drivers, RTOS porting, Board bring up. Prodapt is looking for a Senior Emulation Engineer...

Company: Prodapt
Location: San Jose, CA
Posted Date: 04 Dec 2024

Senior Emulation Engineer

implementation, and debugging during the pre-silicon emulation process. Develop tests to generate complex traffic, performance... scenarios to catch potential post Silicon issues during Pre-Silicon phase. Work with leading emulation vendors to troubleshoot...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 19 Oct 2024

ASIC Design Engineer - Cisco Silicon One

diagnostic and post silicon validation tests in the lab Minimum Qualifications: Bachelor's degree in Electrical or Computer... out of the Milpitas/San Jose office location. Meet the Team Cisco Silicon One (#CiscoSiliconOne) brings together...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 15 Jan 2025
Salary: $133300 - 186800 per year

Principal Engineer - ASIC Validation

for our customers. In this role, you will be responsible for post-silicon validation of ASIC/FPGA including defining & development... · Prior experience with successful post-silicon validation · Ability to triage silicon issues and defining suitable...

Company: Infinera
Location: San Jose, CA
Posted Date: 20 Dec 2024

Senior FPGA Validation

Engineer position is your opportunity to join one of the industry’s leading companies in platform security management... knowledge about FPGAs and computer architecture. As the FPGA Engineer for Axiado, you will have the opportunity to work...

Company: Axiado
Location: San Jose, CA
Posted Date: 15 Jan 2025

SOC / IP Design Verification Engineer

in silicon bring up. We are looking for an adaptive, self-motivative design verification engineer to join our growing team... Integrate VIPs as needed Work with software, validation and emulation teams as needed Work on performance verification. Work...

Posted Date: 16 Jan 2025

Sr. Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation..., DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Senior Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation..., DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...

Company: Prodapt
Location: San Jose, CA
Posted Date: 15 Jan 2025

Senior RTL Design Engineer

validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

Senior Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation..., DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

Sr. Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation..., DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

Senior RTL Design Engineer

validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout...) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based...

Company: Prodapt
Location: San Jose, CA
Posted Date: 14 Jan 2025

IC Design Engineer

system level validation efforts on FPGA/emulation Support silicon bring-up and debug efforts Job Requirements BS+12...Job Description: IC Design Engineer Participate in IP level architectural definition including micro-architecture...

Company: Broadcom
Location: San Jose, CA
Posted Date: 15 Dec 2024
Salary: $119000 - 190000 per year

Senior Asic Design Engineer

-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree in Electrical or Computer Engineering... the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 11 Jan 2025

Senior Design Verification (DV) Engineer

on Linux / Unix Experience with Emulation and FPGA Prototyping Experience with Post-silicon lab bring-up Experience with C/C... silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With approximately...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 07 Jan 2025

ASIC Engineer

is filled or if a sufficient number of applications are received. The Common Hardware Group (CHG) delivers the silicon, optics... Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the...

Company: Cisco Systems
Location: San Jose, CA
Posted Date: 07 Dec 2024