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Keywords: Lead Engineer - PT System Integration, Location: Bangalore, Karnataka

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Lead Engineer - PT System Integration

/ MSEE General Requirements 1) Thorough knowledge of System Architecture & Integration in EV domain. 2) Brief knowledge..., flexibility, security, cost, quality and timelines. 2) Lead the development of electrical powertrain architecture design...

Posted Date: 01 Feb 2025

MTS Silicon Design Engineer ( SOC PD Front End Integration (FEINT) Lead )

_ SOC PD Front End Integration (FEINT) Lead THE ROLE: The scoping of SOC PD FEINT (Front End Integration) lead includes...-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective...

Posted Date: 16 Jan 2025

Full chip SoC timing lead

, PT-PX for Power signoff Should have worked as a go to person or technical lead for at least few full chip projects..._ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Physical Design...

Posted Date: 28 Dec 2024

MTS Silicon Design Engineer

_ MTS SILICON DESIGN ENGINEER SOC PD - Front End Integration (FEINT) Lead THE ROLE: The scoping of SOC PD FEINT (Front... End Integration) lead includes Synthesis, Logic Equivalence, low power check, Timing Closure and full-chip SDC...

Posted Date: 12 Jan 2025

SMTS Silicon Design Engineer

, PT-PX for Power signoff Should have worked as a go to person or technical lead for at least few full chip projects..._ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Physical Design...

Posted Date: 09 Nov 2024

Senior Staff STA CAD Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact About Marvell Marvell is empowering... system-level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud, enterprise...

Company: Marvell
Posted Date: 29 Nov 2024

Associate II - VLSI AL CAD

from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor...

Company: UST
Posted Date: 09 Jan 2025

Associate II - VLSI

from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes... of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: * As an Individual contributor...

Company: UST
Posted Date: 07 Dec 2024

Associate III - VLSI

and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using... relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time...

Company: UST
Posted Date: 07 Dec 2024

Associate III - VLSI

and on-time On time quality delivery approved by the project lead/manager Measures of Outcomes: * Quality –verified using... relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time...

Company: UST
Posted Date: 07 Dec 2024