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Keywords: PLL Design Engineer, Location: Santa Clara, CA

Page: 1

PLL Design Engineer

_ THE ROLE: We are looking for an adaptive, self-motivative logic design engineer to join our growing PLL team. As a key...: Proven experience in analog mixed-signal design from specification to successful silicon experienced in PLL, High Speed...

Posted Date: 29 Mar 2025

Senior Mask Design Engineer - Hardware

, to amplify human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer... role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and multifaceted...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Apr 2025
Salary: $104000 - 195500 per year

Senior Mask Design Engineer - Hardware

, to amplify human creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design... Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 18 Apr 2025

Principal Analog Mixed Signal IC Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Principal... Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 26 Mar 2025
Salary: $165630 - 248100 per year

Senior Principal Analog Design Engineer

in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes. Ability..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Principal Analog Design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 28 Feb 2025

Analog Design, Senior Staff Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog Design Engineer... of innovation in the field of High Speed SerDes Links. What You Can Expect As an analog circuit design engineer...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 02 Feb 2025
Salary: $128160 - 192000 per year

Senior Photonic Layout Design Engineer

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who... chip layout circuit design, circuit checking, and device evaluation and characterization. Responsible for chip floorplan...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 31 Jan 2025

Staff System Design Engineer

functionality. What You Can Expect As a Hardware and Silicon Validation Staff Engineer at Marvell, you’ll be helping to deliver... to ensure product’s quality. Characterize electrical parameters and building blocks such as Tx jitters, CDR loops, CTLE, PLL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $102880 - 154100 per year

Analog IC Design Engineer, Senior Staff

-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally... understanding of analog mixed-signal design with experience in high-speed transceivers. Solid understanding and experience...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Apr 2025
Salary: $140350 - 210200 per year

Analog IC Design Engineer, Staff

budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask... design for implementation. And finally, with the team, you will drive designs into volume production and delight customers...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Apr 2025
Salary: $118900 - 178100 per year

Analog Mixed-Signal Design Engineer

Design, develop, and characterize embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL..., etc. Design and debug RTL level signal synchronization, clock tree and conduct cross domain clock designs. Work closely...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 04 Apr 2025
Salary: $151091 - 155000 per year

RF/Analog IC Design Engineer

with designing RF/Analog circuits for wireless products (e.g., LNA's, PLL's) and 4+ years of ASIC design, verification, or related...Job Description: Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group RFIC Design...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 03 Apr 2025

Senior Mixed Signal Design Engineer

needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal.... What you'll be doing: Lead design and implementation of high speed interface circuit Design projects include high speed...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 13 Mar 2025

Analog Mixed-Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O, SerDes...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $105000 - 135000 per year

Analog IC Design, Principal Engineer

budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask... design for implementation. And finally, with the team, you will drive designs into volume production and delight customers...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $165630 - 248100 per year

Sr. Analog Mixed-Signal Design Engineer

, FIFO, CDR, PLL etc. Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock...Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O, SerDes...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $120000 - 155000 per year

Wireless Systems Engineer

of experience with designing RF/Analog circuits for wireless products (e.g., LNA's, PLL's) and 4+ years of ASIC design, verification.... Join us our Wireless Systems Engineering Team! As a Qualcomm Wireless Systems Engineer, you have the opportunity to push the boundaries...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 03 Apr 2025

IP Enablement Engineer

portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Intel Foundry... will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry...

Company: Intel
Location: Santa Clara, CA
Posted Date: 10 Apr 2025

Staff Silicon Validation Engineer

considerations and PLL/DLL/CDR/ADC/DAC architectures. Experience in high-speed I/O design and testing, particularly with electrical...'s internal IPs, such as High-Speed SerDes, PLL/DLL, and ADCs. Feature Evaluation and Firmware Development: Assess and debug new...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 20 Feb 2025
Salary: $102880 - 154100 per year