with RTL coding using Verilog/VHDL/system Verilog Familiar with the Synthesis and Formal Verification Simulation debugging... Engineering General Summary: Job Spec: Understand Video Codec specification for respective blocks Micro-architect of sub...
will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification... production Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power...