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Keywords: RTL Power design engineer, Location: Bangalore, Karnataka

Page: 6

GPU SOC Design Engineer

verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power...Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation...

Company: Intel
Posted Date: 19 Feb 2025

GPU Design Verification Engineer

and implements corrective measures to resolve failing tests. Collaborates with GPU architects, RTL developers, and physical design..., and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams...

Company: Intel
Posted Date: 19 Feb 2025

SoC Design Verification Engineer

. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power... architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural...

Company: Intel
Posted Date: 19 Feb 2025

Senior Physical Design Engineer

PD methodology and library validation Role: The individual would work in Design Enablement team for Physical Design... flow and library validation. This includes RTL to GDS2 integration validation of test blocks implemented with different...

Posted Date: 05 Feb 2025

Principal Digital Design Engineering

, Inc. is looking for a Power Methodology Design Engineer, Principal to join our Digital Business Unit. The candidate... architecture specifications. Design and implement low power techniques including RTL and UPF design Lead PPA analysis and power...

Posted Date: 06 Apr 2025

Design Verification- IP/DDR/USB

and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL..._ MTS SILICON DESIGN ENGINEER THE ROLE: The candidate will get to work on the Verification of complex PLLs...

Posted Date: 20 Mar 2025

Associate II - VLSI-Physical Design-SV

Job Description: · Physical Design Engineer Experience: 4- 7 Years Desired Skills and Experience: · Engineers... Flow fand able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low...

Company: UST
Posted Date: 15 Mar 2025

Manager Silicon Design Engineering

_ MANAGER – SILICON DESIGN ENGINEER THE ROLE: AMD seeks a passionate, collaborative leader with strong technical skills.... Experience in clocking, reset, power-up sequences and power management verification. Understanding of low power design...

Posted Date: 22 Feb 2025

Physical Design Lead

_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new...: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing...

Posted Date: 21 Feb 2025

Sr. Manager Silicon Design Engineering

_ SENIOR MANAGER SILICON DESIGN ENGINEER THE ROLE: The ideal candidate will get to work on Verification of complex Analog... verification methodology is an added advantage. UPF based RTL low power verification Prior experience in working on IPs...

Posted Date: 08 Feb 2025

Architect Digital Design

-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large variety... of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...

Company: onsemi
Posted Date: 06 Feb 2025

Architect Digital Design

and analog/mixed-signal products. As Senior Principal / Staff Engineer, you will define the design platform, targeting a large... variety of different products. Your responsibilities will include architecture definition, design specification, RTL modeling...

Company: onsemi
Posted Date: 06 Feb 2025

Senior STA Engineer

design Implementation RTL to GDSII : Synopsys/Cadence tools. Familiar with LVF/POCV variation formats and understanding... Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers...

Company: Intel
Posted Date: 10 Apr 2025

Staff Engineer, ASIC development engineering (SOC DV)

in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment.... Job Description SoC Verification Engineer The SoC Development team at Sandisk is seeking highly motivated SoC Verification Engineers...

Company: SanDisk
Posted Date: 09 Apr 2025

CPU Verification Engineer/Lead

to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding...Job Details: Job Description: Role and Responsibilities You will be part of Intel Core Design Team driving Intel...

Company: Intel
Posted Date: 09 Apr 2025

Senior CAD Engineer

do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC...Role Overview We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts...

Company: Aeva
Posted Date: 05 Apr 2025

Senior Silicon Engineer

Engineer. You will join our front-end silicon team and be responsible for delivering cutting-edge, high performance, low power..., you will be responsible for RTL micro-architecture and design, solving complex problems in a datacenter. You will interact with the software...

Company: Microsoft
Posted Date: 04 Apr 2025

Sr. Electrical Engineer

world communicates. Requisition ID: 74531 Senior Digital IC Design Engineer Seeking an experienced Digital IC design... engineer for architecting and developing complex mixed signal ICs for Power, Isolation and Infrastructure applications...

Company: Skyworks
Posted Date: 27 Mar 2025

DFX Engineer- 8+ years

_ SMTS SILICON DESIGN ENGINEER Circuit Technology team is looking for a passionate and experienced DFT Methodology... anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good...

Posted Date: 26 Mar 2025

STA Timing Engineer- 11+ years

_ SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role will involve driving the physical design flow from timing... through final sign-off, collaborating closely with cross-functional teams to meet stringent power, performance, and area (PPA...

Posted Date: 26 Mar 2025