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Keywords: Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer, Location: San Francisco, CA

Page: 1

Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer

Job Summary: We are seeking a skilled CAD Infrastructure Lead to support our ASIC design team. The ideal candidate... will be responsible for developing and maintaining the CAD infrastructure, ensuring efficient design workflows, and supporting the design...

Company: Capgemini
Location: San Francisco, CA
Posted Date: 02 Feb 2025