Job Title: Senior DV Engineer Job Location: San Francisco CA Job Description We are seeking Senior Design... Verification Engineer for our Full Time role with Capgemini Engineering. Key Responsibilities: Work on subsystems with multiple...
Job Title: RTL Engineer Job Location: San Francisco CA Job Description We are seeking Digital Design/RTL Design... engineer for our Full Time Employment with Capgemini Engineering. Key Responsibilities: Perform detailed block design...
Job Role: Physical Design (Synthesis) Engineer Job Location : San Jose CA Job Description At least 7+ years... of experience in ASIC/SOC project design and development Hands on with Cadence tools, DFT flow & physical aware flow Prior...
Job Description Title : Sr Sales Executive Semiconductor Services Chip Design Location: SFO, Bay Area, California... with semiconductor clients through comprehensive solutions in chip design, software, hardware, supply chain, and sustainability. Key...
Job description: Capgemini Engineering is looking for a strong Senior Analog Layout Engineer, who will be working... and complete layouts, ensuring seamless integration and optimal performance Run physical design/reliability verification, debug...
Job description: Senior Analog Layout Engineer will be responsible for layout of high-performance analog cores... industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. · Must be able to set up...