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Keywords: Senior IP Logic Design Engineer, Location: Santa Clara, CA

Page: 1

Senior IP Logic Design Engineer

level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design... Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Senior IP Design Verification Engineer

. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs... Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Senior Staff Hardware Design Engineer

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Hardware Design Senior Staff... and expertise in electrical circuit design for power supply, clock distribution, control logic functions, and in basic communication...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 22 Feb 2025
Salary: $143200 - 214500 per year

Design Verification, Senior Staff Engineer

Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data... development and execution. As a senior member in the team, he/she will focus on improving the design verification methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Jan 2025
Salary: $121840 - 182500 per year

ASIC/RTL Design Engineer - Senior (US)

, SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

, SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

PMTS Silicon Design Engineer

_ PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a seasoned SoC Architect with expertise or significant interest... optimization, along with power impact at architecture, logic design, and circuit levels Excellent communication, management...

Posted Date: 15 Feb 2025

Senior DFx Architect and RTL/Methodology Engineer

logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power... ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs, RTL coding...

Posted Date: 09 Jan 2025