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Keywords: Staff ASIC Design Engineer – Constraints & RTL, Location: Ottawa, ON

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Staff ASIC Design Engineer – Constraints & RTL

. Develop synthesis and timing constraints for complex block and sub-systems Design and implement complex RTL logic (mainly... / principal IC Design Engineer with the following... Minimum of an undergraduate degree in EE or equivalent skills/experience...

Location: Ottawa, ON
Posted Date: 15 Feb 2025