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Keywords: Digital Design (RTL) Engineer, Location: Santa Clara, CA

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Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer

Job Role: RTL Engineer Job Location: Santa Clara CA Job description: We are seeking Digital Design (RTL) engineer... for our full time role with Capgemini Engineering. Minimum 10 years of strong experience in Digital design at RTL level using...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Jan 2025

Digital Design (RTL) Engineer

Role: Digital Design (RTL) Engineer Location: Santa Clara, CA -Remote work option allowed... Job Description: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro...

Posted Date: 25 Jan 2025

Memory RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... Digital design and RTL coding Timing Synthesis & Drive Physical implementation Collaborate with architects, hardware...

Posted Date: 30 Jan 2025

Sr Logic Design RTL Engineer

: Sr Logic Design (RTL) Engineer Location: Santa Clara, CA (Remote and Hybrid options available) Job Type: Contract... in Logic (RTL) Design Proficiency in Verilog/System Verilog/VHDL Strong fundamentals in VLSI design, digital design...

Company: PDDN INC.
Location: Santa Clara, CA
Posted Date: 25 Jan 2025
Salary: $78 per hour

Memory RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware... Digital design and RTL coding Timing Synthesis & Drive Physical implementation Collaborate with architects, hardware...

Posted Date: 18 Dec 2024

Sr. Logic Design (RTL) Engineer

Location: San Clara, California. Job description: The RTL Engineer performs detailed block design from system.../CPF). Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc. Knowledge of JESD204C...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Nov 2024
Salary: $110000 - 200000 per year

Senior RTL Analysis Methodology Engineer

Methodology Engineer to join our dynamic and growing team. If you like solving challenging problems in asynchronous digital design... design methodology! We're responsible for the RTL CDC and RDC methodology for all of NVIDIA's semiconductor products...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 17 Nov 2024

Senior Staff Engineer - Digital IC Design

, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Engineer, Digital... IC Design with Marvell, you’ll be a member of the Automotive business group. In Automotive BG, you will be involved...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 30 Jan 2025
Salary: $124160 - 186000 per year

Digital Design Engineer, Senior Staff

manager to define block micro-architecture and write design specification. Implement a specification using RTL coding... with focus on front-end complex RTL design Programming skills in Verilog Must be familiar with all stages of the ASIC design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $124160 - 186000 per year

Senior Circuit Design Engineer - Power Modeling and Simulation

We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling and Simulation to join our dynamic..., mixed-signal RTL+spice, s-parameters, etc. Familiarity/experience with industry -standard design and EDA tools (Cadence...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 15 Jan 2025

Senior ASIC Design Engineer

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented.... What you’ll be doing: Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 12 Dec 2024

Circuits Physical Design Engineer

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll.... As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block...

Company: Apple
Location: Santa Clara, CA
Posted Date: 23 Nov 2024

SoC Design Engineer

Minimum MSEE, or equivalent OR BSEE, or equivalent, plus 2 years of digital design experience Familiar with digital... design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of high...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 23 Jan 2025
Salary: $110600 - 135000 per year

Sr./Staff ASIC Design Engineer

, system Verilog, C or C++ languages, digital image processing and chip-level tape out procedure from initial PRD, design...Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test...

Company: OmniVision
Location: Santa Clara, CA
Posted Date: 15 Jan 2025
Salary: $130000 - 200000 per year

Sr. Staff Physical Verification CAD Engineer

advanced CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation... and methodologies for digital and analog IC design, verification, and physical implementation. Proficiency with tools such as Cadence...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 18 Jan 2025
Salary: $113480 - 170000 per year

Graphics FE Integration Engineer

. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural... parameters, physical constraints, DFT logic and power intent. Description Description As a GPU Design Integration Engineer...

Company: Apple
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $121900 - 183600 per year

CPU Gate Level Synthesis/Verification Engineer

design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... Experience in digital logic design Experience with formal verification or simulation tools Experience with a scripting language...

Company: Apple
Location: Santa Clara, CA
Posted Date: 22 Dec 2024

CPU Gate Level Synthesis/Verification Engineer

design team in block level verification runs and debug • Running synthesis on the RTL to find potential gate-level issues... Experience in digital logic design Experience with a scripting language Key Qualifications Key Qualifications Preferred...

Company: Apple
Location: Santa Clara, CA
Posted Date: 22 Dec 2024

CPU Processor Power Management Verification Engineer

architecture, or power management architecture Experience with digital design verification including knowledge of Verilog/System...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Nov 2024

CPU Processor Power Management Verification Engineer

Minimum Qualifications Minimum BS Computer architecture knowledge Digital design knowledge including using Verilog for digital design...? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Nov 2024
Salary: $121900 - 183600 per year