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Keywords: RTL Design Engineer, Location: Cupertino, CA

Page: 1

RTL Design Engineer

chain-of-thought reasoning. RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring... development. Experience with high-speed digital logic. Proficiency in standard RTL design and synthesis tools Familiarity...

Company: Etched
Location: Cupertino, CA
Posted Date: 19 Feb 2025
Salary: $2000 per month

Mixed-Signal Clocking and Control RTL Design Engineer

Clocking and Control RTL Design position on our team. As a valued member of this group, you will have the opportunity... and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal...

Company: Apple
Location: Cupertino, CA
Posted Date: 01 Mar 2025

Mixed-Signal Clocking and Control RTL Design Engineer

Clocking and Control RTL Design position on our team. As a valued member of this group, you will have the opportunity... and phase interpolators. The logic design will involve working with multiple clocks, complex clock domain crossings, signal...

Company: Apple
Location: Cupertino, CA
Posted Date: 01 Mar 2025

Physical Design Methodology Engineer, Annapurna Labs

learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the... and visualizing QoR/stats - Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve...

Company: Amazon
Location: Cupertino, CA
Posted Date: 26 Feb 2025
Salary: $129800 per year

Sr. Physical Design Engineer, Annapurna Labs

Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right... and teamwork with other physical design engineers as well as with the RTL/Arch. teams About the team Inclusive Team Culture...

Company: Amazon
Location: Cupertino, CA
Posted Date: 26 Feb 2025
Salary: $143300 per year

Physical Design Engineer

chain-of-thought reasoning. Physical Design Engineer Etched is looking for exceptional PD engineers to join our team... Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025
Salary: $2000 per month

SoC Design/Integration & Synthesis Engineer

& Synthesis Engineer, you will have responsibilities spanning various aspects of SOC design: - Drive all front-end integration... RTL logic design or implementation experience on multi-million gate ASICs will be a plus Ability to communicate...

Company: Apple
Location: Cupertino, CA
Posted Date: 19 Feb 2025

Design Verification Engineer

that no one has solved yet? Do you like changing the game? We have an opportunity for an outstandingly hardworking design... verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft...

Company: Apple
Location: Cupertino, CA
Posted Date: 14 Feb 2025

ASIC Design Engineer - Neural Engine DMA

impact getting functional products to millions of customers quickly. Description Description As an ASIC Design Engineer...). In this front-end design role, your tasks will include: - Coding high-quality RTL, with embedded assertions and cover points...

Company: Apple
Location: Cupertino, CA
Posted Date: 25 Jan 2025
Salary: $121900 - 183600 per year

ASIC Design Engineer - Pixel IP

Engineer in the Pixel IP design team, you will work closely with many multi-functional teams (chip integration, physical design... Qualifications Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog. Extensive shown...

Company: Apple
Location: Cupertino, CA
Posted Date: 10 Jan 2025

ASIC Design Engineer - Neural Engine DMA

impact getting functional products to millions of customers quickly. Description Description As an ASIC Design Engineer...). In this front-end design role, your tasks will include: - Coding high-quality RTL, with embedded assertions and cover points...

Company: Apple
Location: Cupertino, CA
Posted Date: 04 Jan 2025

DDR Design Engineer

Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming.... We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer...

Company: Apple
Location: Cupertino, CA
Posted Date: 07 Dec 2024

FPGA Designer (Display Silicon Digital Architect)

. Description Description - Work with multi-functional teams to converge on display silicon functionality - Use existing silicon and design FPGAs... Architecture, RTL Coding, Implementation, Verification, Debugging and Deployment Experience with serial interfaces like SPI, I2C...

Company: Apple
Location: Cupertino, CA
Posted Date: 06 Mar 2025

SoC Power Flow Methodology Engineer

of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team..., you'll help deliver cutting-edge new technology and capabilities for low-power chip design that fuels Apple's next-generation...

Company: Apple
Location: Cupertino, CA
Posted Date: 06 Mar 2025
Salary: $121900 - 183600 per year

Sr. SoC Power Engineer, Annapurna Labs, Cloud Scale Machine Learning

by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power... & modelling at various stages of design (RTL to gate level netlist) - Develop and maintain dashboards for power rollups - Work...

Company: Annapurna Labs
Location: Cupertino, CA
Posted Date: 04 Mar 2025
Salary: $143300 per year

Senior Software Development Engineer, Annapurna Labs, Trainium Collectives

We are seeking an experienced engineer to work on distributed AI/ML systems. This role involves working on collective... experts, hardware engineers, RTL engineers, scientists & architects. Our workforce spans the globe and is truly international...

Company: Annapurna Labs
Location: Cupertino, CA
Posted Date: 04 Mar 2025
Salary: $151300 per year

Performance Modeling Engineer

integration with infrastructure, thorough testing, and debugging. Collaborate closely with architecture, RTL design, design... architecture, SoC design, and RTL languages. Experience solving ambiguous problems. Excellent verbal and written communication...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025

ASIC Timing Engineer

chain-of-thought reasoning. ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer... analysis and closure of chips at block, cluster, and full chip level Collaborate with Physical Design, DFX, Clocks...

Company: Etched
Location: Cupertino, CA
Posted Date: 20 Feb 2025
Salary: $2000 per month

Senior Software Development Engineer, Annapurna Labs, Trainium Collectives

DESCRIPTION We are seeking an experienced engineer to work on distributed AI/ML systems. This role involves working... experts, hardware engineers, RTL engineers, scientists & architects. Our workforce spans the globe and is truly international...

Company: Amazon
Location: Cupertino, CA
Posted Date: 12 Feb 2025
Salary: $151300 per year

Software Development Engineer, HPC/ML Interconnect Engineer, Annapurna Labs

DESCRIPTION We are seeking an experienced engineer to work on distributed AI/ML systems. This role involves working... experts, hardware engineers, RTL engineers, scientists & architects. Our workforce spans the globe and is truly international...

Company: Amazon
Location: Cupertino, CA
Posted Date: 11 Feb 2025
Salary: $129300 per year