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Keywords: IP Design Verification Engineer, Location: Santa Clara, CA

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IP Design Verification Engineer

. The IP Design Verification Engineer performs functional verification of IP logic to ensure design will meet specification... to microarchitecture specifications. In addition, the IP Design Verification Engineer: Executes verification plans and defines and runs...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Senior IP Design Verification Engineer

but not limited to: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development... developing bus functional models for unit level verification or Verification IP development Preferred skills and experience...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

Design Verification, Senior Staff Engineer

Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data... development and execution. As a senior member in the team, he/she will focus on improving the design verification methodology...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Jan 2025
Salary: $121840 - 182500 per year

ASIC Design Verification Engineer (Santa Clara, CA)

technologies and products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The... in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 23 Jan 2025

Senior IP Logic Design Engineer

level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design... through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

ASIC Design Verification (Santa Clara, CA)

Verification Engineer The team is responsible for the complete verification lifecycle, from system-level concept to tape out... IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 16 Feb 2025
Salary: $107400 - 161200 per year

Design Quality and Reliability Engineer

. In this position, you will be part of the Pre-Silicon Design Quality and Reliability Engineer (Pre-Si QRE) group, supporting the... development of CPU and Hard IPs on the most advanced Intel processes. The Pre-Silicon Design Quality and Reliability Engineer...

Company: Intel
Location: Santa Clara, CA
Posted Date: 19 Feb 2025

PMTS Silicon Design Engineer

_ PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a seasoned SoC Architect with expertise or significant interest... amongst design teams, marketing, and business unit executives. THE PERSON: You have excellent communication and presentation...

Posted Date: 15 Feb 2025

Memory RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware..., complex processor architecture, digital design, and verification in general. You are a team player who has excellent...

Posted Date: 30 Jan 2025

Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer

, configuration registers, etc. Knowledge of JESD204C block design and related design/verification experience (includes licensed IP...Job Role: RTL Engineer Job Location: Santa Clara CA Job description: We are seeking Digital Design (RTL) engineer...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Jan 2025

CPU Physical Design and Integration Engineer

quickly. Description Description As a CPU Physical Design and Integration Engineer, you will be participating in the... physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jan 2025

CPU Physical Design and Integration Engineer

quickly. Description Description As a CPU Physical Design and Integration Engineer, you will be participating in the... physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan...

Company: Apple
Location: Santa Clara, CA
Posted Date: 17 Jan 2025

Memory RTL Design Engineer

_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware..., complex processor architecture, digital design, and verification in general. You are a team player who has excellent...

Posted Date: 18 Dec 2024

Sr. Logic Design (RTL) Engineer

block design and related design/verification experience (includes licensed IP & PHY from 3rd parties) Awareness of DFT...Location: San Clara, California. Job description: The RTL Engineer performs detailed block design from system...

Company: Capgemini
Location: Santa Clara, CA
Posted Date: 29 Nov 2024
Salary: $110000 - 200000 per year

ASIC/RTL Design Engineer - Senior (US)

; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification..., SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 14 Feb 2025

ASIC/RTL Design Engineer - Senior (US)

; - Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification..., SATA and Client internal IP's. Successful candidates will be responsible for leading, and participating in, the design...

Company: Managed Staffing
Location: Santa Clara, CA
Posted Date: 13 Feb 2025

Digital Design Engineer, Senior Staff

. We develop the architecture, collaborate on IP development, create the physical design, and work with the world’s leading AI data... techniques and best practices Work with the physical design teams for synthesis and timing signoff. Work with the Verification...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 16 Jan 2025
Salary: $124160 - 186000 per year

Sr Sales Executive Semiconductor Chip Design Engineering Services

of semiconductor ecosystem, including relationships with foundries, EDA companies, and IP providers. · Background in ASIC Design...Job Description Title : Sr Sales Executive Semiconductor Services Chip Design Location: SFO, Bay Area, California...

Posted Date: 19 Feb 2025

CPU Physical Electrical Analysis Engineer

next groundbreaking Apple product! As a CPU Physical Electrical Analysis Engineer, you will be driving the block and top level design.... Description Description Drive block and top-level EMIR/electrical verification closure • Work on power grid design, construction, and implementation...

Company: Apple
Location: Santa Clara, CA
Posted Date: 10 Jan 2025

CPU Physical Electrical Analysis Engineer

next groundbreaking Apple product! As a CPU Physical Electrical Analysis Engineer, you will be driving the block and top level design.... Description Description Drive block and top-level EMIR/electrical verification closure • Work on power grid design, construction, and implementation...

Company: Apple
Location: Santa Clara, CA
Posted Date: 09 Jan 2025